Patent Literature 1 discloses a semiconductor device connected to a sub-mount via a solder layer. Electrode layers are respectively provided on upper and lower surfaces of the semiconductor device. The lower-surface-side electrode layer is connected to a metal thin film provided on an upper surface of the sub-mount via the solder layer. Instead of being formed in an entire area of the lower surface of the semiconductor device, the lower-surface-side electrode layer is not formed at end portions of the lower surface in a longitudinal direction, and those end portions of the semiconductor layer are exposed. The solder layer has poor wettability with respect to the semiconductor layer and has favorable wettability with respect to an electrode layer. Therefore, the solder layer does not adhere onto both end portions of the semiconductor device, and a rise of the solder (climb) to side surfaces of the semiconductor device (including the laser emission surface) is prevented from occurring (see, for example, paragraphs [0010], [0017], and [0029] and FIGS. 1A 1B, 1C, 2, and 6 of Patent Literature 1).
An electronic apparatus disclosed in Patent Literature 2 includes an electronic component (semiconductor chip), a printed board on which a noble metal layer is printed, and a solder for bonding them. A back-surface electrode of the semiconductor chip and the noble metal layer of the printed board are bonded by the solder. The noble metal layer is provided in a continuous annular shape so as to surround a projection area (component projection area) of the semiconductor chip. At the time of solder bonding, the melted solder wettedly spreads along the noble metal layer in a continuous annular shape surrounding an entire outer circumference of the component projection area, so a solder thickness is apt to become uniform at the four corners of the component projection area. Therefore, when the semiconductor chip is mounted, the semiconductor chip is prevented from being tilted (see, for example, paragraphs [0052], [0078], and [0079], and FIGS. 1A, 1B, and 1C of Patent Literature 1).